I. Field of the Invention
The present invention relates generally to junction isolated semiconductor devices and relates more particularly to methods for preventing parasitic mechanisms in such devices.
II. Description of the Related Art
One of the disadvantages of BiPOLAR and Field Effect Transistor (FET) junction isolated technologies is the feature that makes it useful, namely the junction isolation. The problem specifically relates to the difficulty in maintaining proper biasing of the substrate/isolation-active region junctions to 20 ensure that the N side of a P-N junction remains at a higher potential (i.e., reverse biased) relative to the P side. Improper biasing may cause integrated circuit (IC) device malfunction and/or destruction during reverse voltage conditions.
The prior art mainly subscribes to fixed voltage biasing of 25 the isolation regions. However, as in the case of a P-type isolated device, an output pin voltage more negative than the isolation voltage may cause device failure. Also, when the output also has to sustain a reverse battery supply condition, device failure is more probable than not. This condition can occur, for example, in automotive electronics when battery cables are reversed. The detrimental effect is that the junctions become forward biased and parasitic mechanisms such as transistor or diode action occurs. This leads to malfunction and destruction of the desired integrated circuit components. Thus a need exists for a means of preventing parasitic forward biasing of substrate/isolation-active region PN junctions.
The words substrate/isolation used together, in the context of this application simply indicate that the isolation regions are of the same conductivity as the underlying substrate, and are continuous. That is, there is no physical separation between them. The term "substrate/isolation-active" is a term which is used only with the word "region" following the word "active", and simply refers to the junction between the substrate/isolation and the active regions.